The trend in the integrated circuit industry is toward the fabrication of integrated circuit devices having increased levels of performance. One method of achieving higher performance is to reduce the electrical resistance of the components in the integrated circuit. Typically, a metal-oxide-semiconductor (MOS) transistor includes a polycrystalline silicon gate electrode, and source and drain regions residing in a silicon substrate. The performance of an MOS transistor can be improved by reducing the electrical resistance within the transistor. One method for reducing the electrical resistance is to heavily dope both the gate electrode and the source and drain regions with a dopant, such as arsenic, phosphorus, and boron. However, once the solid solubility limit of the dopant is reached, the electrical resistance is not reduced by the further addition of dopants to the silicon substrate. Accordingly, integrated circuit designers employ refractory metal silicides to further reduce the electrical resistance and increase the performance.
Although the use of refractory metal silicides has led to improved device performance, the presence of low resistance silicide regions has reduced the ability of integrated components to withstand high voltage and current transients caused by an electrostatic discharge. This is true in part because the lower electrical resistance of the silicided regions enables the device to conduct a large electrical current. During an electrostatic discharge event, a transient voltage pulse can cause a large current to be conducted through an MOS transistor and into thin metal leads. The high electrical current can be sufficient to the melt metal leads, and to create voids in the interconnect metallization. Further, the high current levels can conglomerate the silicide in the source and drain regions creating current leakage paths. Thus, in the worst case, the thermal affects of the electrostatic discharge event can cause complete device failure.
One method of reducing the deleterious affects of an electrostatic discharge event is to provide protection devices in the integrated circuit. Typically, a protection device, such as a diffused resistor, or a gate-clamped MOS transistor, is provided between an input-output (I/O) pad and sensitive circuit elements. However, the ability of the protection devices to prevent transient voltage spikes from being transmitted from the I/O pad to a sensitive circuit is compromised if the protection device also contains silicided components. Accordingly, a silicide blocking layer is placed over functional regions of the protection device to prevent the silicidation of the protection devices.
Although the formation of a silicide blocking layer is effective in preventing the silicidation of protection devices, the processing steps necessary to form the blocking layer can result in substantial degradation of the substrate and overlying dielectric layers. Accordingly, improved processing methods are necessary to enable the formation of silicide blocking layers in an electrostatic discharge protection device.